RVINT - Integer Mathematical library for RISC-V
WAT is even happening in the picture
It is clear that my poor giraffe does not have the M instruction set for division and multiplication instructions, even though it does appear to have some kind of “auxiliary leg” extension.
To help the giraffe, I have written RVINT - a library of integer mathematical operations for RISC-V processors, targeting the base RV32I and RV64I microcontroller instruction sets.
The routines are designed to be as concise as possible to allow them to be used in embedded execution environments, while also being reasonably efficient. PRs are welcome.
An example - dividing 123456 by 123:
li a0, 123456 # Load dividend (123456) into a0
li a1, 123 # Load divisor (123) into a1
jal divremu # unsigned 64/32 bit division/remainder
# at this point, a0 contains the quotient, 1003
# and a1 contains the remainder, 87The following operations are supported:
Division
On 32-bit processors
32-bit by 32-bit signed and unsigned division with 32-bit result and remainder.
On 64-bit processors
64-bit by 64-bit signed and unsigned division with 64-bit result and remainder.
Multiplication
On 32-bit processors:
32-bit by 32-bit signed and unsigned multiplication with 32-bit result.
32-bit by 32-bit signed and unsigned multiplication with 64-bit result.
on 64-bit processors:
32-bit by 32-bit signed and unsigned multiplication with 64-bit result.
64-bit by 64-bit signed and unsigned multiplication with 64-bit result.
64-bit by 64-bit signed and unsigned multiplication with 128-bit result.
Base Conversions & I/O Operations
These operations support 32-bit numbers on 32-bit architectures and 64-bit numbers on 64-bit architectures.
ASCII binary to binary.
ASCII unsigned decimal to binary.
ASCII signed decimal to two's complement binary.
ASCII hexadecimal to binary.
binary to ASCII binary.
two's complement binary to ASCII signed decimal.
unsigned binary to unsigned ASCII decimal.
binary to ASCII hexadecimal.
Square Root
32-bit integer square root on 32-bit processors.
64-bit integer square root on 64-bit processors.
Greatest Common Divisor
32-bit GCD of two unsigned 32-bit numbers on 32-bit processors.
64-bit GCD of two unsigned 64-bit numbers on 64-bit processors.
Least Common Multiple
32-bit LCM of two unsigned 32-bit numbers on 32-bit processors.
64-bit LCM of two unsigned 64-bit numbers on 64-bit processors.
Bit Operations
Count leading zeroes in 32-bit number on 32-bit processors.
Count leading zeroes in 64-bit number on 64-bit processors.
Count trailing zeroes in 32-bit number on 32-bit processors.
Count trailing zeroes in 64-bit number on 64-bit processors.